Design a memory-test system to test the first 256 bytes

Design a memory-test system to test the first 256 bytes of a static RAM memory. The system consists of simple controller, an 8-bit counter, a comparator, and a memory as shown subsequently. The counter is connected to both the address and data (IO) bus so that 0 will be written to address 0, 1 to address 1, 2 to address 2, . . ., and 255 to address 255. Then the data will be read back from address 0, address 1, . . ., address 255 and compared with the address. If the data does not match, the controller goes to the fail state as soon as a mismatch is detected; otherwise, it goes to a pass state after all 256 locations have been matched. Assume that OE_b = 0 and CS_b = 0.
(a) Draw an SM chart or a state graph for the controller (five states). Assume that the clock period is long enough so that one word can be read every clock period.
(b) Write Verilog code for the memory-test system.

A Verilog module has inputs A and B and outputs

A Verilog module has inputs A and B and outputs C and D. A and B are initially high. Whenever A goes low, C will go high 5 ns later, and if A changes again, C will change 5 ns later. D will change if B does not change for 3 ns after A changes. The timing checks should be done inside: specify …. Endspecify 

(a) Write the Verilog module with an always block that determines the outputs C and D.
(b) Write another always block to check that B is stable 2 ns before and 1 ns after A goes high. The always block should also report an error if B goes low for a time interval less than 10 ns.

Hamming codes are used for error detection and correction in

Hamming codes are used for error detection and correction in communication and memory systems. Error detection and correction capability is incorporated in these codes by inserting extra bits into the data word. Addition of one parity bit can detect odd number of bit flips, but no error correction is possible with one parity bit. A (7,4) Hamming code has 4 bits of data but 7 bits in total, including the 3 parity bits. It can detect two errors and correct one error. This code can be constructed as follows: If we denote data bits as d4d3d2d1, the encoded code word would be d4d3d2p4d1p2p1, where p4, p2, and p1 are the added parity bits. These bits must satisfy the following conditions for even parity:

p4 = d2 XOR d3 XOR d4;……………………….(1)
p2 = d1 XOR d3 XOR d4;……………………….(2)
p1 = d1 XOR d2 XOR d4;……………………….(3)
When the 7 bits are received/decoded, an error syndrome S3S2S1 is calculated as follows:
p4 XOR d2 XOR d3 XOR d4 = S3;……………………….(4)
p2 XOR d1 XOR d3 XOR d4 = S2;……………………….(5)
p1 XOR d1 XOR d2 XOR d4 = S1;……………………….(6)
The syndrome indicates which bit is wrong. For example, if the syndrome is 110, it indicates that bit 6 from right end (i.e., d3) has flipped. If S3S2S1 is 000, there is no error. 

(a) Is there any error in the code word 0110111? If yes, which bit? What was the original data? What must be the corrected code word?
(b) How will these 6 equations get modified for odd parity? Write the 6 equations for odd parity.
(c) Write a Verilog module for error detection without using tasks. The inputs to the module are the 7-bit encoded data word and the type of parity, and the output is the syndrome. The type of parity is encoded as 0 for odd parity and 1 for even parity.

module error_detector(data, PARITY, Syndrome)
 {
 }

(d) Modify the Verilog module in (c) to use Verilog tasks. Write required Verilog task(s) that will generate the error syndrome given the code word. The input to the task is data, and output is the syndrome. You have to call necessary task(s) for each type of parity.
task error_p(data, Syndrome)
 {
 }

The structural Verilog code that follows is a 2-input NOR

The structural Verilog code that follows is a 2-input NOR gate with the rise/fall time defined as parameters.

module NOR2(a, b, c);
parameter Trise = 3;
parameter Tfall = 2;

parameter load = 1;
input a, b;
output reg c;
wire nor_value;
assign nor_value = ~(a | b);
always @(nor_value)
begin
if(nor_value == 1’b1)
#(Trise + 3*load) c = 1’b1;
else
#(Tfall + 3*load) c = 1’b0;
end
endmodule
module NOR2_TEST(in1, in2, in3, in4, out1, out2);
input in1, in2, in3, in4;
output out1, out2;
NOR2 U1 (in1, in2, out1);
/*
place for your new code
*/
endmodule

(a) Instantiate NOR2 (U2) by using the parameter map method (Trise = 5, Tfall = 4, load = 3).
(b) Use the defparam to pre-define the timing values and instantiate NOR2 (U3), which has rise time = 4, fall time = 3, and load = 2.
(c) What are the rise time, fall time, and fan-out time of U1?
(d) What are the rise and fall delays of NOR2 (U2)?

A clocked T flip-flop has propagation delays from the rising

A clocked T flip-flop has propagation delays from the rising edge of CLK to the changes in Q and Q’ as follows: if Q (or Q’) changes to 1, tplh = 8 ns, and if Q (or Q’) changes to 0, tphl = 10 ns. The minimum clock pulse width is tck = 15 ns, the setup time for the T input is tsu = 4 ns, and the hold time is th = 2 ns. Write a Verilog model for the flip-flop that includes the propagation delay and that reports if any timing specification is violated. Write the model using parameters with default values. The timing checks should be done inside: specify …. Endspecify

Design a memory tester that verifies the correct operation of

Design a memory tester that verifies the correct operation of a 6116 static RAM (Figure 8-15). The tester should store a checkerboard pattern (alternating 0s and 1s.

     K = 1 when counter is in state 255
   Eq = 1 when counter output = data from memory
WEb = 0 enables tristate buffer

in the even addresses, and alternating 1s and 0s in the odd addresses) in all memory locations and then read it back. The tester should then repeat the test using the reverse pattern.
(a) Draw a block diagram of the memory tester. Show and explain all control signals.
(b) Draw an SM chart or state graph for the control unit. Use a simple RAM model and disregard timing.
(c) Write Verilog code for the tester and use a test bench to verify its operation.

Modern microprocessors employ pipelining to improve instruction throughput. Consider a

Modern microprocessors employ pipelining to improve instruction throughput. Consider a 5-stage pipeline consisting of fetch, decode, and read registers along with execute, memory access, and register write-back stages. During the first stage, an instruction is fetched from the instruction memory. During the second stage, the fetched instruction is decoded. The operand registers are also read during this stage. During the third stage, the arithmetic or logic operation is performed on the register data read during the second stage. During the fourth stage, in load/store instructions, data memory is read/written into memory. Arithmetic instructions do not perform any operation during this stage. During the fifth stage, arithmetic instructions write the results to the destination register.
(a) Design a pipelined implementation of the MIPS design shown in Figure 9-8. Draw a block diagram indicating the general structure of the pipeline. Write Verilog code, synthesize it for an FPGA target, and implement it on an FPGA prototyping board. Assume that each stage takes one clock cycle. While implementing on the prototyping board, use an 8-Hz clock as in Problem 9.16. Assume that instruction memory access and data memory access take only one cycle. Instruction and data memories need to be separated (or must have two ports) in order to allow simultaneous access from the first stage and the fourth stage. An instruction can read the operands in the second stage from the register file, as long as there are no dependencies with an incomplete instruction (ahead of it in the pipeline). If such a dependency exists, the current instruction in decode stage must wait until the register data is ready. Each instruction should test for dependencies with previous instructions. 

This can be done by comparing source registers of the current instruction with destination registers of the incomplete instructions ahead of the current instruction. The register file is written into during stage 5 and read from during stage 2. A reasonable assumption to make is that the write is performed during the first half of the cycle and the read is performed during the second half of the cycle. Assume that data written into the destination register during the first half of a cycle can be read by another instruction during the second half of the same cycle. 

(b) How many cycles does it take to execute N instructions with no dependencies?